Job Title: Logic Design Lead
Location: Hudson, MA
Duration: Full time
- 9+ years of experience and Participated in 2-3 SoC projects
- Must have extensive experience in Micro-architecture design at IP/Subsystem level
- Experience in any of the following domain is highly desirable:
PCIe – Gen3/4
Any high speed chip to chip interconnect
- Multi core processor architecture and SIMD processors
- Extensive experience in SoC RTL coding (Verilog or System-Verilog).
- Experience in RTL Code Linting and CDC checks.
- Experience in RTL integration using Industry standard tools, is an added advantage
- Experience in low power design techniques
- Good understanding of DFx design techniques
- Experience in creating and understanding of Design Constraints(SDC files-Clock Freq, Clock Groups, MCP, False Path, Exceptions)